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1-mb (64k x 16) static ram cy62127dv30 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05229 rev. *h revised june 19, 2006 features ? temperature ranges ? industrial: ?40c to 85c ? automotive: ?40c to 125c ? very high speed: 45 ns ? wide voltage range: 2.2v to 3.6v ? pin compatible with cy62127bv ? ultra-low active power ? typical active current: 0.85 ma @ f = 1 mhz ? typical active current: 5 ma @ f = f max ? ultra-low standby power ? easy memory expansion with ce and oe features ? automatic power-down when deselected ? available in pb-free and non pb-free 48-ball fbga and a 44-lead tsop type ii packages functional description [1] the cy62127dv30 is a high-performance cmos static ram organized as 64k words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption by 90% when addresses are not toggling. the device can be put into standby mode reducing power consumption by more than 99% when deselected (ce high or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high) or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes . note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 64k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 2048 x 512 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we ble bhe a 0 a 1 a 9 power -down circuit bhe ble ce a 10 10
cy62127dv30 document #: 38-05229 rev. *h page 2 of 11 product portfolio pin configurations [2, 3] notes: 2. nc pins are not connected to the die. 3. pin #23 of tsop ii and e3 ball of fbga are dnu, which have to be left floating or tied to vss to ensure proper application. ( expansion pins on fbga package: e4 - 2m, d3 - 4m, h1 - 8m, g2 - 16m, h6 - 32m). 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min. typ. max. typ [4] max. typ. [4] max. range typ. [4] max. cy62127dv30l 2.2 3.0 3.6 45 0.85 1.5 6.5 13 ind?l 1.5 5 cy62127dv30ll 45 0.85 1.5 6.5 13 ind?l 1.5 4 cy62127dv30l 2.2 3.0 3.6 55 0.85 1.5 5 10 ind?l 1.5 5 auto 1.5 15 cy62127dv30ll 2.2 3.0 3.6 55 0.85 1.5 5 10 ind?l 1.5 4 cy62127dv30l 2.2 3.0 3.6 70 0.85 1.5 5 10 ind?l 1.5 5 cy62127dv30ll 70 0.85 1.5 5 10 ind?l 1.5 4 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii (forward) 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 dnu v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h fbga (top view) nc dnu v cc nc
cy62127dv30 document #: 38-05229 rev. *h page 3 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ......................................................................... ? 0.3v to 3.9v dc voltage applied to outputs in high-z state [5] .................................... ? 0.3v to v cc + 0.3v dc input voltage [5] ................................ ? 0.3v to v cc + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature (t a )v cc [6] industrial ?40c to +85c 2.2v to 3.6v automotive ?40c to +125c 2.2v to 3.6v dc electrical characteristics (over the operating range) parameter description test conditions ?45 ?55 ?70 unit min. typ. [4] max. min. typ. [4] max. min typ. [4] max. v oh output high voltage 2.2 < v cc < 2.7 i oh = ? 0.1 ma 2.0 2.0 2.0 v 2.7 < v cc < 3.6 i oh = ? 1.0 ma 2.4 2.4 2.4 v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma 0.4 0.4 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma 0.4 0.4 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 v cc + 0.3 1.8 v cc + 0.3 1.8 v cc + 0.3 v 2.7 < v cc < 3.6 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v il input low voltage 2.2 < v cc < 2.7 ? 0.3 0.6 ? 0.3 0.6 ? 0.3 0.6 v 2.7 < v cc < 3.6 ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 i ix input leakage current gnd < v i < v cc ind?l ? 1 +1 ? 1 +1 ? 1 +1 a auto ? 4 +4 a i oz output leakage current gnd < v o < v cc , output disabled ind?l ? 1 +1 ? 1 +1 ? 1 +1 a auto ? 4 +4 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6v, i out = 0 ma, cmos level 6.5 13 5 10 5 10 ma f = 1 mhz 0.85 1.5 0.85 1.5 0.85 1.5 i sb1 automatic ce power-down current? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe and ble ) l ind?l 1.5 5 1.5 5 1.5 5 a auto 1.5 15 ll 1.5 4 1.5 4 1.5 4 i sb2 automatic ce power-down current? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.6v l ind?l 1.5 5 1.5 5 1.5 5 a auto 1.5 15 ll 1.5 4 1.5 4 1.5 4 capacitance [7] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz v cc = v cc(typ) 8pf c out output capacitance 8 pf notes: 5. v il(min.) = ? 2.0v for pulse durations less than 20 ns., v ih(max.) = vcc + 0.75v for pulse durations less than 20 ns. 6. full device operation requires linear ramp of v cc from 0v to v cc(min) & v cc must be stable at v cc(min) for 500 s. 7. tested initially and after any design or proces changes that may affect these parameters.
cy62127dv30 document #: 38-05229 rev. *h page 4 of 11 data retention waveform [10] notes: 8. test condition for the 45-ns part is a load capacitance of 30 pf. 9. full device operation requires linear v cc ramp from v dr to v cc(min.) > 200 s. 10. bhe . ble is the and of both bhe and ble . chip can be deselected by either disabling t he chip enable signals or by disabling both. thermal resistance [7] parameter description test conditions fbga tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 76 c/w jc thermal resistance (junct ion to case) 12 11 c/w ac test loads and waveforms [8] parameters 2.5v (2.2v - 2.7v) 3.0v (2.7v - 3.6v) unit r1 16600 1103 ? r2 15400 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics parameter description conditions min. typ .[4] max. unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc =1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v l ind?l 4 a l auto 10 ll ind?l 3 t cdr [7] chip deselect to data retention time 0 ns t r [9] operation recovery time 200 s v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: equivalent all input pulses r th r1 thevenin t cdr v dr > 1.5v data retention mode t r ce or v cc bhe . ble v cc(min.) v cc(min.) t cdr v dr > 1.5v data retention mode t r ce or v cc bhe . ble v cc(min.) v cc(min.)
cy62127dv30 document #: 38-05229 rev. *h page 5 of 11 switching characteristics (over the operating range) [11] parameter description cy62127dv30-45 [8] cy62127dv30-55 cy62127dv30-70 unit min. max. min. max. min. max. read cycle t rc read cycle time 45 55 70 ns t aa address to data valid 45 55 70 ns t oha data hold from address change 10 10 10 ns t ace ce low to data valid 45 55 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z [12] 555ns t hzoe oe high to high z [12,14] 15 20 25 ns t lzce ce low to low z [12] 10 10 10 ns t hzce ce high to high z [12,14] 20 20 25 ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 45 55 70 ns t dbe ble /bhe low to data valid 45 55 70 ns t lzbe [13] ble /bhe low to low z [12] 555ns t hzbe ble /bhe high to high-z [12,14] 15 20 25 ns write cycle [15] t wc write cycle time 45 55 70 ns t sce ce low to write end 40 40 60 ns t aw address set-up to write end 40 40 60 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 35 40 50 ns t bw ble /bhe low to write end 40 40 60 ns t sd data set-up to write end 25 25 30 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high z [12,14] 15 20 25 ns t lzwe we high to low z [12] 10 10 5 ns notes: 11. test conditions assume signal transition time of 1v/ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol . 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 13. if both byte enables are toggled together, this value is 10 ns. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 15. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write.
cy62127dv30 document #: 38-05229 rev. *h page 6 of 11 switching waveforms read cycle no. 1 (address transition controlled) [16,17] read cycle no. 2 (oe controlled) [16,17,18] write cycle no. 1 (we controlled) [14, 15, 19, 20, 21] notes: 16. device is continuously selected. oe , ce = v il , bhe , ble = v il . 17. we is high for read cycle. 18. address valid prior to or coincident with ce , bhe , ble transition low. 19. data i/o is high-impedance if oe = v ih . 20. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 21. during the don't care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. address data out previous data valid data valid t rc t aa t oha t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce a ddress we data i/o oe bhe /ble t bw don't care
cy62127dv30 document #: 38-05229 rev. *h page 7 of 11 write cycle no. 2 (ce controlled) [14, 15, 19, 20, 21] write cycle no. 3 (we controlled, oe low) [20, 21] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce a ddress we data i/o oe bhe / ble t bw t sa don't care data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce a ddress we data i/o t bw bhe /ble don't care
cy62127dv30 document #: 38-05229 rev. *h page 8 of 11 truth table write cycle no. 4 (bhe -/ble -controlled, oe low) [20, 21] switching waveforms (continued) data i/o a ddress t hd t sd t sa t ha t aw t wc ce we data in valid t bw bhe /ble t sce t pwe don't care ce we oe bhe ble i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z deselect/power-down standby (i sb ) x x x h h high z deselect/power-down standby (i sb ) l h l l l read all bits active (i cc ) l h l h l read lower byte only active (i cc ) l h l l h read upper byte only active (i cc ) l h h l l output disabled active (i cc ) l h h h l output disabled active (i cc ) l h h l h output disabled active (i cc ) high z high z high z data out data out high z high z data out high z high z high z data out high z high z l l x l l data in data in write active (i cc ) l l l l x x h l l h data in high z high z data in write lower byte only write upper byte only active (i cc ) active (i cc )
cy62127dv30 document #: 38-05229 rev. *h page 9 of 11 ordering information speed (ns) ordering code package diagram package type operating range 45 cy62127dv30ll-45bvxi 51-85150 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) industrial cy62127dv30ll-45zxi 51-85087 44-le ad tsop type ii (pb-free) 55 cy62127dv30ll-55bvi 51-85150 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) industrial cy62127dv30ll-55bvxi 51-85150 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) cy62127dv30ll-55zi 51-85087 44-lead tsop type ii cy62127dv30l-55zxi 51-85087 44-le ad tsop type ii (pb-free) cy62127dv30ll-55zxi 51-85087 44-le ad tsop type ii (pb-free) cy62127dv30l-55bvxe 51-85150 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) automotive cy62127dv30l-55zsxe 51-85087 44-le ad tsop type ii (pb-free) 70 cy62127dv30l-70bvi 51-85150 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) industrial cy62127dv30ll-70bvxi 51-85150 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) cy62127dv30l-70zi 51-85087 44-lead tsop type ii cy62127dv30ll-70zxi 51-85087 44-le ad tsop type ii (pb-free) please contact your local cypress sales re presentative for availability of these parts package diagrams a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d
cy62127dv30 document #: 38-05229 rev. *h page 10 of 11 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and mobl2 and more battery life are trademarks of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 44-lead tsop ii (51-85087) 51-85087-*a
cy62127dv30 document #: 38-05229 rev. *h page 11 of 11 document history page document title: cy62127dv30 mobl ? 1-mb (64k x 16) static ram document number: 38-05229 rev. ecn no. issue date orig. of change description of change ** 117690 08/27/02 jui new data sheet *a 127311 06/13/03 mpr changed from ad vanced status to preliminary changed isb2 to 5 a (l), 4 a (ll) changed iccdr to 4 a (l), 3 a (ll) changed cin from 6 pf to 8 pf *b 128341 07/22/03 jui changed from preliminary to final add 70-ns speed, updated ordering information *c 129000 08/29/03 cdy changed icc 1 mh z typ from 0.5 ma to 0.85 ma *d 316039 see ecn pci added 45-ns speed bin in ac, dc and ordering information tables added footnote # 8 on page #4 added lead-free package ordering information on page# 9 changed 44-lead tsop-ii package name from z44 to zs44 *e 346982 see ecn aju added 56-pin qfn package *f 369955 see ecn syt added temperature ranges in the features section on page # 1 added automotive specs for i ix ,i oz ,i sb1 and i sb2 in the product portfolio on page #2 and the dc electrical characteristics table on page# 4 added automotive spec for i ccdr in the data retention characteristics table on page# 5 added pb-free automotive parts for 55 ns speed bin *g 457685 see ecn nxr removed 56-pin qfn package from product offering updated ordering information table *h 470383 see ecn nxr changed pin #23 of tsop ii from nc to dnu and updated footnote #2

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